Publications from MESA

• S. M. Pieper, J. M. Paul, M. J. Schulte "A New Era of Performance Evaluation," IEEE Computer, accepted for publication, Feb 2007.
  
  
• D. R. Janes, M. J. Schulte, E. K. Brodsky, and W. F. Block, "Low Latency Interventional MRI Visualization using a GPU Cluster," Proceedings of the Joint Annual Meeting of ISMRM-ESMRMB (ISMRM 2007), May, 2007 [ pdf format ]  
  
  
• D. R. Janes, M. J. Schulte, E. K. Brodsky, and W. F. Block, "GPU Cluster Multidimensional Visualization: Harnessing Computational Resources for Real-time Medical Visualization," to appear in User Centered Design for Medical Visualization, 2007.
  
  
• M. Cornea, C. Anderson, J. Harrision, P. Tang, E. Schneider, C. Tsen, "A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding," accepted for publication in Proceedings of the IEEE International Symposium on Computer Arithmetic, Montpellier, France, June 2007
  
  
• L.-K. Wang and M. J. Schulte, "Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding," accepted for publication in Proceedings of the IEEE International Symposium on Computer Arithmetic, Montpellier, France, June 2007 [ pdf format ]  
  
  
• M. A. Erle, M. J. Schulte, and B. J. Hickmann "Decimal Floating-Point Multiplication Via Carry-Save Addition," in Proceedings of the IEEE International Symposium on Computer Arithmetic, Montpellier, France, pp. 46-55, June 2007. (Extended version available by request from schulte@engr.wisc.edu) [ pdf format ]  
  
  
• A. K. Polisetti, S. Assadi, C. Deibele, J. Patterson, R. C. McCrady, and M. J. Schulte, "A Digital Ring Transverse Feedback Low-Level RF Control System," accepted for publication in Proceedings of the 22nd Particle Accelerator Conference, June 2007
  
  
• C. Tsen, M. Schulte, S. Gonzalez-Navarro "Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit" in Proceedings of the Eighteenth International Conference Application-specific Systems, Architectures and Processors, Montreal Canada, July 2007 [ pdf format ]  
  
  
• C. Tsen, S. Gonzalez-Navarro, and M. J. Schulte "Hardware Design of a Binary Integer Decimal-based Floating-point Adder" in Proceedings of the Twenty Fifth International Conference on Computer Design, Lake Tahoe CA, October 2007 [ pdf format ]  
  
  
• L. K. Wang, C. Tsen, M. J. Schulte, and D. Jhalani "Benchmarks and Performance Analysis of Decimal Floating-Point Applications" in Proceedings of the Twenty Fifth International Conference on Computer Design, Lake Tahoe, CA, October 2007 [ pdf format ]  
  
  
  

• J. Liu, M.J. Redmond, E.K. Brodsky, A. Lu, F.J. Thornton, T.M. Grist, M. J. Schulte, J.G. Pipe, and W.F. Block, "Generation and Visualization of Four Dimensional MR Angiography Data Using an Under-sampled 3D Projection Trajectory," in IEEE Transactions on Medical Imaging, vol. 25, no. 2, pp. 148-157, February 2006,
  
  
• S. Mamidi, E. R. Blem, M. J. Schulte, J. Glossner, D. Iancu, A. Iancu, M. Moudgill, and S. Jinturkar, "Instruction Set Extensions for Software Defined Radio," accepted for publication in the Journal on Embedded Systems, 2006.
  
  
• P. Garcia, K. Compton, M. J. Schulte, E. Blem, and W. Fu "An Overview of Reconfigurable Computing in Embedded Systems," accepted for publication in the EURASIP Journal on Embedded Systems, 2006.
  
  
• A. Akkas and M. J. Schulte, "Efficient Dual-Mode Floating-Point Multiplier Design and Implementation," accepted for publication in the Journal of Systems Architecture, 2006.
  
  
• K. E. Wires and M. J. Schulte, "Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication," in Journal of VLSI Signal Processing, vol. 42, no. 3, pp. 257-272, March, 2006.
  
  
• M. J. Schulte, J. Glossner, S. Jinturkar, M. Moudgill, S. Mamidi, S. Vassiliadis, "A Low-Power Multithreaded Processor for Software Defined Radio," in the Journal of VLSI Signal Processing (Special Issue Featuring Extended Versions of Best Papers from SAMOS2004), vol. 43, no. 2-3, pp. 143 . 159, June 2006.
  
  
• L.-K. Wang and M. J. Schulte, "A Decimal Floating-Point Divider using Newton-Raphson Iteration," accepted for publication in the Journal of VLSI Signal Processing Systems (Special Issue Featuring Extended Versions of Best Papers from ASAP2004), 2006.
  
  
• M. Gok, M. J. Schulte, and M. G. Arnold, "Integer Multiplier Designs with Overflow Detection," in IEEE Transactions on Computers, vol. 55, no. 8, pp. 1062-1066, August 2006.
  
  
• D. Iancu, H. Ye, J. Glossner, M. J. Schulte, S. Mamidi, and J. Takala, "Improved Spectral Efficiency through Iterative Concatenated Convolutional Reed-Solomon Software Decoding," submitted to the IEEE Transactions on Communications, September 2006
  
  
• S. Mamidi, M. J. Schulte, Z. Xie, M. Sima, D. Iancu, and J. Glossner, "Arithmetic Units for Software Defined Radio," accepted for publication in Proceedings of the Fortieth Asilomar Conference on Signals, Systems, and Computers, November, 2006
  
  
• J. Glossner, D. Iancu, M. Moudgill, G. Nacer, S. Jinturkar, and M. Schulte, "The Sandbridge SB3011 SDR Platform," in Proceedings of the Symposium on Trends in Communications, pp. ii-v, June 2006
  
  
• D. Iancu, H. Ye, J. Glossner, M. J. Schulte, S. Mamidi, and J. Takala, "Improved Spectral Efficiency through Iterative Concatenated Convolutional Reed-Solomon Decoding," accepted for publication in the Proceedings of the IST Symposium on Trends in Communications, pp. 1-5, June 2006
  
  
• M. Sima*, D. Iancu**, J. Glossner**, M. J. Schulte+ and S. Mamidi+, "Software Based Geometry Operations for 3D Computer Graphics," in Proceedings of the SPIE International Symposium on Electronic Imaging: Multimedia on Mobile Devices, San Jose, CA, vol. 6074, pp. 104-112, January 2006
  
  
• S. Mamidi, M. J. Schulte, Z. Xie, M. Sima, D. Iancu, and J. Glossner, .Arithmetic Units for Software Defined Radio,. accepted for publication in Proceedings of J. Glossner, D. Iancu, M. Moudgill, G. Nacer, S. Jinturkar, and M. Schulte, "The Sandbridge SB3011 SDR Platform," in Proceedings of the Symposium on Trends in Communications, pp. ii-v, June 2006
  
  
• D. Iancu, H. Ye, J. Glossner, M. J. Schulte, S. Mamidi, and J. Takala, "Improved Spectral Efficiency through Iterative Concatenated Convolutional Reed-Solomon Decoding," accepted for publication in the Proceedings of the IST Symposium on Trends in Communications, pp. 1-5, June 2006
  
  
• M. Sima*, D. Iancu**, J. Glossner**, M. J. Schulte+ and S. Mamidi+, "Software Based Geometry Operations for 3D Computer Graphics," in Proceedings of the SPIE International Symposium on Electronic Imaging: Multimedia on Mobile Devices, San Jose, CA, vol. 6074, pp. 104-112, January 2006
  
  
• D. R. Janes, M. J. Schulte, E. K. Brodsky, and W. F. Block, "Rapid Vascular Rendering Using 4D Cluster Visualization," ISMRM Workshop on Real-Time MRI: Dynamic Interactive Imaging and its Applications, Santa Monica, CA, February, 2006 [ pdf format ]  
  
  
• S. Mamidi, M. J. Schulte, D. Iancu, and J. Glossner, "Reconfigurable Multithreaded Processors for Programmable Communication Systems," submitted to the International Symposium on Computer Architecture, November, 2006
  
  
• M. Cornea, C. Anderson, C. Tsen "Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic," International Conference on Software and Data Technologies, September 2006
  
  
  

• M. J. Schulte, J. Glossner, S. Jinturkar, M. Moudgill, S. Mamidi, and S. Vassiliadis, "A Low-Power Multithreaded Processor for Software Defined Radio," accepted for publication in the Journal of VLSI Signal Processing, vol. 41, 2005. [ pdf format ]  
  
  
• J. Glossner, S. Dorward, S. Jinturkar, M. Moudgill, E. Hokenek, M. Schulte, and S. Vassiliadis, "Sandbridge Software Tools," in Proceedings of the 5th Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, Lecture Notes in Computer Science, Vol. 3553, Samos, Greece, pp. 269-278, July, 2005 [ pdf format ]  
  
  
• S. Mamidi, E. R. Blem, M. J. Schulte, J. Glossner, D. Iancu, A. Iancu, M. Moudgill, and S. Jinturkar, "Instruction Set Extensions for Software Defined Radio on a Multithreaded Processor," in Proceedings of the ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems, San Jose, CA, pp. 266-273, September 2005. [ pdf format ]  
  
  
• J. Glossner, M. Moudgill, D. Iancu, G. Nacer, S. Jintukar, S. Stanley, M. Samori, T. Raja, M. J. Schulte, and S. Vassiliadis, "Future Wireless Convergence Platforms" in Proceedings of the IEEE/ACM/IFIP International Conference on Hardware-Software Codesign and System Synthesis, New York, September, pp. 7-12, 2005. [ pdf format ]  
  
  
• M. J. Schulte, N. Lindberg, and A. Laxminarain "Performance Evaluation of Decimal Floating-Point Arithmetic, " in Proceedings of the 6th IBM Austin Center for Advanced Studies Conference, Austin, TX, February, 2005. [ pdf format ]  
  
  
• R. D. Kenney and M. J. Schulte, "High-Speed Decimal Multioperand Adders" in IEEE Transactions on Computers, vol. 54, no. 8, pp. 953- 963, August 2005. [ pdf format ]  
  
  
• L.-K. Wang and M. J. Schulte, "Decimal Floating-Point Square Root Using Newton-Raphson Iteration " Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Samos, Greece, pp. 309-315, July 2005. [ pdf format ]  
  
  
• S. Mamidi, D. Iancu, A. Iancu, M. J. Schulte, and J. Glossner, "Instruction Set Extensions for Reed-Solomon Encoding and Decoding" in Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Samos, Greece, pp. 364-369, July 2005. [ pdf format ]  
  
  
• M. A. Erle, E. M. Schwarz, and M. J. Schulte, "Decimal Multiplication with Efficient Partial Product Generation," in Proceedings of the IEEE International Symposium on Computer Arithmetic, pp. 21-28, Cape Cod, MA, June 2005. [ pdf format ]  
  
  
• E. G. Walters and M. J. Schulte, "Efficient Function Approximation Using Truncated Multipliers and Squarers" in Proceedings of the IEEE International Symposium on Computer Arithmetic, pp. 232-239, Cape Cod, MA, June 2005. [ pdf format ]  
  
  
• J. E. Stine and M. J. Schulte, "A Combined Two’s Complement and Floating-Point Comparator," in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 89-92, May 2005. [ pdf format ]  
  
  
• Liang-Kai Wang and Michael J. Schulte "A Decimal Floating-Point Divider Using Newton-Raphson Iteration" Submitted to Journal of VLSI Signal Processing
  
  
• B. H. Meyer, J. J. Pieper, J. M. Paul, J. E. Nelson, S. M. Pieper, A. G. Rowe, "Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors," IEEE Transactions on Computers, June 2005
  
  
• M. J. Schulte, S. Bhattacharyya, and R. Schreiber, "Guest Editorial," Special Issue of the Journal of VLSI Signal Processing on Application-Specific Systems, Architectures, and Processors, vol. 40, pp. 5-6, May 2005
  
  
• M. J. Schulte and J.-C. Bajard, "Guest Editors Introduction: Special Issue on Computer Arithmetic," IEEE Transactions on Computers, vol. 54, pp. 241-242, no. 3, March 2005
  
  
• E. R. Blem, S. Mamidi, M. J. Schulte, J. Glossner, D. Iancu, M. Moudgill, and S. Jinturkar, "Instruction Set Extensions for Cyclic Redundancy Check on a Multithreaded Processor," in the Workshop on Media and Streaming Processors, Barcelona, pp. 36-42, November, 2005
  
  
  

• R. D. Kenney, M. J. Schulte, and M. A. Erle "High-Frequency Decimal Multiplier" Proceedings of the IEEE International Conference on Computer Design, pp. 26-29, San Jose, CA, October 2004. [ pdf format ]  
  
  
• L.-K. Wang and M. J. Schulte "Decimal Floating-Point Division Using Newton-Raphson Iteration" Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 84-95, Galveston, TX, September 2004. [ pdf format ]  
  
  
• S. Krithivasan, M. J. Schulte, and J. Glossner, "A Subword-Parallel Multiplication and Sum-of-Squares Unit," in Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Lafayette, LA, pp. 273-274, February, 2004. [ pdf format ]  
  
  
• M. Redmond, E. Brodsky, Y.-H. Hu, T. Grist, M. J. Schulte, and W. Block, "The 4D Cluster Visualization Project," in Proceedings of the SPIE International Symposium on Medical Imaging, San Diego, CA, vol. 5367, pp. 28-38, February, 2004.
  
  
• R. D. Kenney and M. J. Schulte "Multioperand Decimal Addition" Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 251-253, Lafayette, LA, February, 2004. [ pdf format ]  
  
  
• J. Thompson, N. Karra, and M. J. Schulte "A 64-bit Decimal Floating-Point Adder" Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 297-298, Lafayette, LA, February, 2004. [ pdf format ]  
  
  
• M. J. Schulte, K. Chirca, J. Glossner, H. Wang, S. Mamidi, P. I. Balzola, and S. Vassiliadis, "A Low-Power Carry Skip Adder with Fast Saturation," Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 269-279, Galveston, TX, September 2004. [ pdf format ]  
  
  
• J. Riley and M. J. Schulte "A Hardware Accelerator for Elliptic Curve Cryptography over GF(2^m)" International Journal of Computer Research - Special Issue on Cryptographic Hardware and Embedded Systems, 2004. [ pdf format ]  
  
  
• K. Chirca, M. Schulte, J. Glossner, S. Mamidi, and S. Vassiliadis, "A Static Low-Power, High-Performance 32-bit Carry Skip Adder," Proceedings of the 2004 Euromicro Symposium on Digital System Design, pp. 615-619, Rennes, France, September, 2004. [ pdf format ]  
  
  
• J. Glossner, K. Chirca, M. J. Schulte, H. Wang, N. Nasimzada, D. Har, S. Wang, A. J. Hoane, Jr., G. Nacer, M. Moudgill, and S. Vassiliadis, "Sandbridge Sandblaster Low Power DSP" Proceedings of the IEEE Custom Integrated Circuits Conference, Orlando, FL, October 2004. [ pdf format ]  
  
  
• M. Gok, M. J. Schulte, and S. Krithivasan, "Designs for Subword-Parallel Multiplications and Dot Product Operations," Proceedings of the Workshop on Application Specific Processors, pp. 27-31, Stockholm, Sweden, August, 2004.
  
  
• E. G. Walters, M. J. Schulte, and M. G. Arnold, "Truncated Squarers with Constant and Variable Correction," Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, Denver, Colorado, August, 2004. [ pdf format ]  
  
  
• M. J. Schulte, J. Glossner, S. Mamidi, M. Moudgill, and S. Vassiliadis, "A Low-Power Multithreaded Processor for Baseband Communication Systems, " Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, Lecture Notes in Computer Science, Springer, vol. 3133, pp. 393-402, July 2004. [ pdf format ]  
  
  
• J. Glossner, M. J. Schulte, M. Moudgill, S. Jinturkar, T. Raja, G. Nacer, and S. Vassiliadis, "Sandblaster Low-Power Multithreaded SDR Baseband Processor," Proceedings of the Workshop on Application Specific Processors, pp. 53-60, Stockholm, Sweden, August, 2004. [ pdf format ]  
  
  
• X. Yang, S. K. Valia, M. J. Schulte and R. B. Lee, "Exploration and Evaluation of PLX Floating-point Instructions and Implementations for 3D Graphics," Proceedings of the Thirty Eight Asilomar Conference on Signals, Systems, and Computers, November, 2004. [ pdf format ]  
  
  
  

• M. G. Arnold, J. E. Garcia, and M. J. Schulte, "The Interval Logarithmic Number System," in Proceedings of the 16th IEEE Symposium on Computer Arithmetic, Santiago de Compostela, Spain, IEEE Computer Society Press, pp. 253-261, June 2003. [ pdf format ]  
  
  
• M. J. Schulte, L. P. Marquette, S. Krithivasan, E. G. Walters, and J. Glossner, "Combined Multiplication and Sum of Squares Units," in Proceedings of the IEEE International Conference on Application- Specific Systems, Architectures, and Processors, the Hague, Netherlands, IEEE Computer Society Press, pp. 204-214, June, 2003. (One of three finalists for the best paper award). [ pdf format ]  
  
  
• M. A. Erle and M. J. Schulte, "Decimal Multiplication Via Carry-Save Addition," in Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, the Hague, Netherlands, IEEE Computer Society Press, pp. 348-358, June, 2003. [ pdf format ]  
  
  
• M. Senthilvelan and M. J. Schulte, "A Flexible Arithmetic and Logic Unit for Multimedia Processing," in Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, pp. 520-528, San Diego, California, August, 2003. [ pdf format ]  
  
  
• E. Walters III, M. G. Arnold, and M. J. Schulte, "Using Truncated Multipliers in DCT and IDCT Hardware Accelerators," in Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, pp. 573-584, San Diego, California, August, 2003. [ pdf format ]  
  
  
• A. Akkas and M. J. Schulte, "A Quadruple Precision and Dual Double Precision Floating-Point Multiplier," in Proceedings of the 2003 Euromicro Symposium on Digital System Design, pp. 76-81, Antalya, Turkey, September, 2003 [ pdf format ]  
  
  
• S. Krithivasan and M. J. Schulte, "Multiplier Architectures for Media Processing," in Proceedings of the Thirty Seventh Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, IEEE Press, pp. 2193-2197, November, 2003. [ pdf format ]  
  
  
• S. Mamidi, M. Senthilvelan, M. J. Schulte, and S. Krithivasan, "Automated Generation of Configurable Media Processors," in Proceedings of the Thirty Seventh Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp. 339-343, IEEE Press, November, 2003. [ pdf format ]  
  
  
  

• J. Glossner, M. Schulte, and S. Vassailiadis, "A Java-enabled DSP," in Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, Lecture Notes in Computer Science, Springer, vol. 2268, pp. 307-326, 2002. [ pdf format ]  
  
  
• M. R. Pillmeier and M. J. Schulte, "Design Alternatives for Barrel Shifters and Rotators," in Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations, vol. 4791, pp. 436-447, Seattle, Washington, July, 2002. [ pdf format ]  
  
  
• E. G. Walters and M. J. Schulte, "Design Tradeoffs Using Truncated Multipliers in FIR Filter Implementations," in Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations, Seattle, Washington, vol. 4791, pp. 357-368, July, 2002. [ pdf format ]  
  
  
• J. E. Garcia and M. J. Schulte, "A Combined 16-Bit Binary and Dual Galois Field Multiplier," in Proceedings of the IEEE Workshop on Signal Processing Systems, San Diego, California, pp. 63-68, October, 2002. [ pdf format ]  
  
  
• M. A. Erle, M. J. Schulte, and J. G. Linebarger, "Potential Speedup with Decimal Floating-Point Hardware," in Proceedings of the Thirty Sixth Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, IEEE Press, pp. 1073-1077, November, 2002. [ pdf format ]  
  
  
  

• J. Glossner, D. Routenberg, E. Hokenek, M. Moudgill, M. Schulte, P. I. Balzola, and S. Vassailiadis, "Towards Very High Bandwidth Wireless Battery Powered Devices," in IEEE Computer Society Workshop on VLSI, Orlando, Florida, IEEE Computer Society Press, pp. 3-9, April, 2001. [ pdf format ]  
  
  
• K. C. Bickersta , E. E. Swartzlander, Jr., and M. J. Schulte, "Analysis of Column Compression Multipliers," in Proceedings of the 15th IEEE Symposium on Computer Arithmetic, Vail, Colorado, IEEE Computer Society Press, pp. 33-39, June 2001. [ pdf format ]  
  
  
• N. Koc-Sahan, J. Schlessman, and M. J. Schulte, "Symmetric Table Addition Methods for Neural Network Approximations," in Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations XI, San Diego, CA, pp. 126-133, July, 2001. [ pdf format ]  
  
  
• K. E. Wires, M. J. Schulte, and D. McCarley, "FPGA Resource Reduction Through Truncated Multiplication," in Proceedings of the 11th International Conference on Field Programmable Logic and Applications, Belfast, Ireland, pp. 574-583, August, 2001. [ pdf format ]  
  
  
• K. E. Wires, M. J. Schulte, and J. E. Stine, "Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation," in Proceedings of the International Conference on Computer Design, Austin, TX, IEEE Computer Society Press, pp. 497-500, September, 2001. [ pdf format ]  
  
  
• P. I. Balzola, M. J. Schulte, J. Ruan, and J. Glossner, and E. Hokenek, "Design Alternatives for Parallel Saturating Multioperand Adders," in Proceedings of the International Conference on Computer Design, Austin, TX, IEEE Computer Society Press, pp. 172-177, September, 2001. [ pdf format ]  
  
  
• M. Gok, M. J. Schulte, and P. I. Balzola, "Efficient Integer Multiplication Overflow Detection Circuits," in Proceedings of the Thirty Fifth Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, IEEE Press, pp. 1661-1665, November, 2001. [ pdf format ]  
  
  
• E. G. Walters, J. Schlessman, and M. J. Schulte, "Combined Unsigned and Two's Complement Hybrid Squarers," in Proceedings of the Thirty Fifth Asilomar Conference on Signals, Systems, and Comput- ers, Pacific Grove, California, IEEE Press, pp. 861-866, November, 2001. [ pdf format ]  
  
  
  

• D. Batten, S. Jinturkar, J. Glossner, M. Schulte, and P. D'arcy, "A New Approach to DSP Intrinsic Functions," in Proceedings of the IEEE Thirty-Third Hawaii International Conference on System Sciences, Hawaii, January, pp. 2892-2901, 2000. [ pdf format ]  
  
  
• J. Hormigo, J. Villalba, and M. Schulte, "A Hardware Algorithm for Variable-Precision Division," in Proceedings of the 4th Conference on Real Numbers and Computers, pp. 104-112, Dagstuhl, Germany, April, 2000. [ pdf format ]  
  
  
• A. Goldovsky, B. Patel, M. Schulte, R. Kolagotla, H. Srinivas, and G. Burns, "Design and Implementation of a 16 by 16 Low Power Two's Complement Multiplier," in Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland vol. 5, pp. 345-348, May, 2000. [ pdf format ]  
  
  
• J. Hormigo, J. Villalba, and M. Schulte, "A Hardware Algorithm for Variable-Precision Logarithm," in Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Boston, pp. 215-224, IEEE Computer Society Press, July, 2000. [ pdf format ]  
  
  
• M. Schulte, M. Gok, P. Balzola, and R. Brocato, "Combined Unsigned and Two's Complement Saturating Multipliers," in Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations, San Diego, CA, pp. 185-196, July, 2000. [ pdf format ]  
  
  
• M. J. Schulte, P. I. Balzola, J. Ruan, and J. Glossner, "Parallel Saturating Multioperand Adders," in Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, ACM Press, San Jose, California, pp. 172-179, November, 2000. [ pdf format ]  
  
  
• K. E. Wires, M. J. Schulte and J. E. Stine, "Variable-Correction Truncated Floating Point Multipliers," in Proceedings of the Thirty Fourth Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp. 1344-1348, IEEE Press, November, 2000. [ pdf format ]  
  
  
• M. J. Schulte, P. I. Balzola, A. Akkas, and R. W. Brocato, "Integer Multiplication with Overflow Detection or Saturation, " IEEE Transactions on Computers, vol. 49, pp. 681-691, July, 2000. [ pdf format ]  
  
  
• M. J. Schulte and E. E. Swartzlander, Jr., "A Family of Variable-Precision, Interval Arithmetic Processors" IEEE Transactions on Computers, no. 5, vol. 49 pp. 387-398, May, 2000. [ pdf format ]  
  
  
  

• M. J. Schulte, J. G. Jansen, and J. E. Stine, "Reduced Power Dissipation Through Truncated Multiplication," in Proceedings of the IEEE Alessandro Volta Memorial International Workshop on Low Power Design, Como, Italy, pp. 61-69, March, 1999. [ pdf format ]  
  
  
• N. Yadav, M. J. Schulte, and J. Glossner, "Parallel Saturating Fractional Arithmetic Units," in Proceedings of the Ninth Great Lakes Symposium on VLSI, Ann Arbor, Michigan, pp. 214-217, March, 1999. [ pdf format ]  
  
  
• M. J. Schulte and K. E. Wires, "High-Speed Inverse Square Roots," in Proceedings of the 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, pp. 124-131, April, 1999. [ pdf format ]  
  
  
• M. J. Schulte, A. Akkas, V. Zelov, and J. C. Burley, "Compiler Support for Interval Arithmetic," in Proceedings of the 16th IEEE Instrumentation and Measurement Technology Conference, Venice, Italy, pp. 1189-1193, May, 1999. [ pdf format ]  
  
  
• M. J. Schulte and K. E. Wires, "Efficient Second Order Approximations for Reciprocals and Square Roots," in Proceedings of SPIE : Advanced Signal Processing Algorithms, Architectures, and Implementations, vol. 3807, pp. 10-18, Denver, July, 1999. [ pdf format ]  
  
  
• K. E. Wires, M. J. Schulte, L. P. Marquette, and P. I. Balzola, "Combined Unsigned and Two's Complement Squarers," in Proceedings of the Thirty Third Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp. 1215-1219, October, 1999. [ pdf format ]  
  
  
• M. J. Schulte, C. Power, C. Andrews, T. Hamilton, W. Muniz, H. Haileselassie, W. Haileselassie, K. Mlodossich, C. Leveque, E. Smith, and A. Bristol, "National Society of Black Engineers Community Outreach Program," in Proceedings of the 1999 Frontiers in Education Conference, San Juan, Puerto Rico, pp. 12d4-1--12d4-6, November, 1999. [ pdf format ]  
  
  
• M. J. Schulte, "Computer Architecture Web Page Design Projects," in Proceedings of the 1999 Frontiers in Education Conference, San Juan, Puerto Rico, pp. 12a4-18 -- 12a6-21, November, 1999 [ pdf format ]  
  
  
• D. Batten, S. Jinturkar, J. Glossner, M. Schulte, R. Peri and P. D'arcy, "Interactions Between Optimizations and a New Type of DSP Intrinsic Function," in Proceedings of the International Conference on Signal Processing Applications and Technologies, Orlando, Florida, November, 1999. Shortened version published as D. Batten and P. D'arcy, Intrinsic Functions Boost Compilers , in Electrical Engineering Times, p. 104, vol. 1085, November, 1999. [ pdf format ]  
  
  
• M. J. Schulte and James E. Stine, "Approximating Elementary Functions with Symmetric Bipartite Tables" IEEE Transactions on Computers}, no. 8, vol. 48, pp. 842-847, August, 1999. [ pdf format ]  
  
  
• J. E. Stine and M. J. Schulte, "The Symmetric Table Addition Method for Accurate Function Approximation," Journal of VLSI Signal Processing, vol. 21, no. 2, pp. 167-177, June, 1999. [ pdf format ]  
  
  
• M. J. Schulte, A. Akkas, V. Zelov, and J. C. Burley, "The Interval-Enhanced GNU Fortran Compiler," Reliable Computing, vol. 5., no. 3, pp. 311-322, 1999. [ pdf format ]  
  
  
  

• J. E. Stine and M. J. Schulte, "A Combined Interval and Floating Point Multiplier," in Proceedings of 8th Great Lakes Symposium on VLSI, Lafayette, LA, pp. 208-213, February, 1998. [ pdf format ]  
  
  
• J. E. Stine and M. J. Schulte, "A Combined Interval and Floating Point Divider," in Proceedings of the Thirty Second Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, vol. 1, pp. 218-222, November, 1998. [ pdf format ]  
  
  
  

• M. J. Schulte and James E. Stine, "Symmetric Bipartite Tables for Accurate Function Approximation," in Proceedings of the 13th IEEE Symposium on Computer Arithmetic, Pacific Grove, California, pp. 175- 183, July, 1997. [ pdf format ]  
  
  
• M. J. Schulte and James E. Stine, "Accurate Function Approximations by Symmetric Table Lookup and Addition," in Proceedings of the 11th International Conference on Application-Specific Systems, Architectures, and Processors, Zurich, Switzerland, pp. 144-153, July, 1997. [ pdf format ]  
  
  
• M. J. Schulte, J. E. Stine, and K. E. Wires, "High-Speed Reciprocal Approximations ," in Proceedings of the Thirty First Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp. 1183-1187, November, 1997. [ pdf format ]  
  
  
  

• M. J. Schulte, K. C. Bickersta , and E. E. Swartzlander, Jr., "Hardware Designs for Interval Multiplication," in Proceedings of the II Workshop on Computer Arithmetic, Interval and Symbolic Computation, Recife, Brazil, pp. 85-87, August, 1996.
  
  
  

• M. J. Schulte and E. E. Swartzlander, Jr., "Designs and Applications for Variable-Precision, Interval Arithmetic Coprocessors," Reliable Computing, International Workshop on Applications of Interval Computations, El Paso, Texas, pp. 166-172, February, 1995.
  
  
• M. J. Schulte and E. E. Swartzlander, Jr., "A Processor for Staggered Interval Arithmetic," in Proceedings of the 1995 International Conference on Application Specific Array Processors, Strasbourg, France, pp. 104-112, July, 1995. [ pdf format ]  
  
  
• M. J. Schulte and E. E. Swartzlander, Jr., "Hardware Designs and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor," in Proceedings of the 12th IEEE Symposium on Computer Arithmetic, Bath, England, pp. 222-229, July, 1995. [ pdf format ]  
  
  
• T. Lynch, A. Ahmed, M. Schulte, T. Callaway, and R. Tisdale, "The K5 Transcendental Functions," in Proceedings of the 12th IEEE Symposium on Computer Arithmetic, Bath, England, pp. 163-171, July, 1995. [ pdf format ]  
  
  
• M. J. Schulte and E. E. Swartzlander, Jr., "A coprocessor for accurate and reliable numerical computations," in Proceedings of the International Conference on Computer Design, Austin, TX, pp. 686-691, October, 1995. [ pdf format ]  
  
  
  

• M. J. Schulte and E. E. Swartzlander, Jr., "A Variable-Precision, Interval Arithmetic Processor," in Proceedings of the 1994 International Conference on Application Specific Array Processors, San Francisco, pp. 248-258, September, 1994. [ pdf format ]  
  
  
  

• M. J. Schulte and E. E. Swartzlander, Jr., "Exact Rounding of Certain Elementary Functions," in Proceedings of the 11th IEEE Symposium on Computer Arithmetic, Windsor, Ontario, Canada, pp. 138- 145, July, 1993. [ pdf format ]  
  
  
• M. J. Schulte and E. E. Swartzlander, Jr., "Truncated Multiplication with Correction Constant," in VLSI Signal Processing VI, IEEE Workshop on VLSI Signal Processing, Eindhoven, Netherlands, pp. 388-396, October, 1993. [ pdf format ]  
  
  
• K. C. Bickersta , M. J. Schulte, and E. E. Swartzlander, Jr., "Reduced Area Multipliers," in Proceedings of the 1993 International Conference on Application Specific Array Processors, Venice, Italy, pp. 478- 489, October, 1993. [ pdf format ]  
  
  
  

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